• Introduction
• Programme
• Speaker Profiles
• *** Slides ***

Prof. Sir Alec Broers

Mike Muller

James Collier

Mike Harwood

CMOS technologies have traditionally been associated with digital designs where millions of logic gates can be integrated onto a single device and clocked at hundreds of MHz. Bipolar and Bi-CMOS technologies are the preferred choice for analogue designers since bipolar device bandwidth and offset performance is superior. Advanced CMOS processes allow a new generation of mixed analogue and digital designs running at Giga-Hertz frequencies. This lecture highlights some of the challenges of mixed-signal design and describes some of the possible solutions to these problems.

Mike Harwood has worked in the area of CMOS mixed-signal design for the last 13 years, the last 11 years being at Texas Instruments. Most of his time has been spent in the area of data communication concentrating on physical layer interfaces from 4/16Mb/s token-ring to Ethernet and SONET/SDH.

Colin Walls

As SoC designs become more complex, the tools that enable them to be implemented become increasingly critical. It may be argued that it is the tools that make SoC possible in the first place. The capacity of development tools is stressed by the latest designs, but not yet exceeded. The real challenges come with verification.

The design of an SoC is a subtle blend of hardware and software functionality; the two disciplines come together more closely than ever before. This requires a new approach. The need to carry out as much verification and debug prior to the availability of silicon also changes the available methodologies.

This paper reviews the challenges and the resulting verification and debug flow for complex SoC designs, taking into account both hardware and software perspectives.

Colin Walls has worked on software for real-time and embedded systems for more than 20 years. His particular interest is the ever-changing boundary between software and hardware in complex electronic systems. Colin is a frequent presenter at conferences and seminars and author of numerous papers and articles.

Pat Mead

Programmable Logic used to be known for low density, low speed and high cost. Things have changed, and with millions of gates and GHz speeds now available, designers are now looking to so-called SOPCs - Systems on Programmable Chips - to help with the time to market and design issues of SoC projects. Paul Hollingworth, Altera's European Marketing Director, will look at the current state of the industry.

Pat Mead has worked for Altera for 2 years and is responsible for its Technical Marketing functions within Europe. Prior to joining Altera, he worked for two years in Technical Marketing with Lucent Technologies microelectronics group. Pat started his career as an engineer and spent 8 years designing telecommunications systems based around Programmable Logic for both Fujitsu and Marconi. He has a degree in Electronic Engineering from the University of Kent.

Simon Duggins

Simon has 15 years experience of IC and system design at both engineering and management level gained at ICL, Fujitsu, Symbionics and Tality(Cadence) in a wide range of application areas - mainframe CPUs, graphics processors, digital TV and wireless communications (Bluetooth, 802.11). His current role encompasses the management of both Core IP development projects and SOC design projects. Simon has a BSc in Computer Engineering from University of Manchester, and a DipBA from Aston University.

Chris Turner

Chris will present insights into the semiconductor marketplace and indicate some of the technology and business factors affecting Delegate's plans, now and in the future. This will be supported by examining trends such as the emergence of foundry services, fabless companies, IP block exchange, System on Chip and Platform Based Design. In closing, Chris will invite all the Speakers to join a general Q&A session to wrap up the seminar.

Chris Turner is an independent technology consultant based in Cambridge and working in the semiconductor industry. Chris is a founder of Virata Corporation where he was VP of Operations and previously he worked at the Olivetti Research Laboratory and Acorn Computers, where he was one of the BBC Micro designers. Chris was also a design engineer at Philips and at Cambridge University's Cavendish Laboratory. Chris holds a CEI Pt. II qualification and is a Chartered Engineer and IEE Fellow.